1. Technical Field
The present invention is directed toward a layout for ternary CAM bitcells that allows a greater density in an array of CAM bitcells.
2. Description of the Related Art
Content addressable memory (CAM) is a specialized type of memory. Unlike random access memory (RAM), where one uses a given address to randomly access the data stored there, CAM has the capability to supply an address, based on the value stored at or associated with the address. Additionally, an array of CAM cells will have built-in comparison circuitry for every cell of hardware memory. This allows a massively parallel search, where every bit in memory is searched simultaneously. Consequently, the hardware can provide an extremely fast search of a large set of information.
This makes CAMs suitable for applications where fast searches are required, such as imaging, voice recognition, and networking applications. In networking applications, for instance, CAMs are used to control the traffic of packets on the Internet and make sure that the proper information arrives at its destination as specified in the header (e.g. an URL or email address). In many network systems, stand-alone CAM products are used, which then interface, for example, with an application specific integrated circuit (ASIC) to provide the proper function. However, in order to reduce system cost, power consumption and improve performance, there is a desire to embed CAM functionality within an ASIC as a system-on-chip solution. Therefore, there is a strong need to develop high-density, high-performance CAM bitcells. Present layouts do not meet this need, for reasons that will be discussed.
Short Lesson in CAM Circuitry
CAMs are typically derived from a high-density 6T-SRAM bitcell, so an understanding of the circuitry of a bitcell can aid in understanding the complexities of a CAM array. FIG. 1 discloses a circuit diagram of a 6T-SRAM bitcell 100. The bitcell 100 consists of two PMOS transistors P1, P2, four NMOS transistors N1, N2, N3, N4, two bitlines BL, /BL for signal detection, one wordline WL used for reading and writing data to the cell, and the power supplies Vdd, Vss. Bitlines BL, /BL (read as bar BL and shown with an overline in the figures) carry complementary values, i.e., one is high and one is low. When the cell is written, it will contain a single bit of information, e.g., BL=low, /BL=high gives a value of zero while BL=high, /BL=low gives a value of one. The data is stored through two, cross-coupled inverters, with this configuration allowing the information to be maintained without the need for constantly refreshing, as is the case in DRAM. Although other bitcell circuits have been proposed and used, the 6T-SRAM cell shown is the one most commonly used in the industry for bitcells, especially for high-density applications.
Two types of CAM bitcells can be formed from this 6T SRAM bitcell: binary and ternary, which will be explained along with their structures. FIG. 2 discloses a binary CAM (BCAM) bitcell 200. BCAM bitcell 200 will not only store the bit of information in the SRAM structure above, here denoted 202, but also contains two complementary hitlines HBL, /HBL that provide the data for comparison, comparison circuit 204, composed of four additional NMOS transistors N5, N6, N7, N8 that compare the cell data to the hitlines HBL, /HBL, and a matchline ML that indicates if there is a match or not. Because the bitcell, like the SRAM cell above, can have a value of only zero or one, a comparison between the value carried in the bitcell and the value carried in the hitlines can only result in two answers: match or no-match.
More recently, ternary CAM (TCAM) bitcells have been developed that can provide an additional option, an “I don't care” value. To add this extra possible choice, the TCAM contains two 6T-SRAM bitcells and their respective programming circuits, although no additional hitlines are added. FIG. 3 discloses a TCAM bitcell 300. Bitcell 300 contains two 6T-SRAM bitcells 302A, 302B, but only one comparison circuit 304 and associated hitlines HBL, /HBL. Table 1 below shows the possible values for BCAM cells, while Table 2 shows possible values for TCAM cells.
TABLE 1BCAMBL/BLCell Value010101
TABLE 2TCAMBL1/BL1BL2/BL2Cell Value010100110Don't care1001Not used10101As discussed previously, a binary CAM has only two values and will either match or not match against the hitlines. In the ternary CAM, there are four possible combinations of values shown by the bitline, although one of the possible values, with both BL1 and /BL2 high, is not used. When both BL1 and /BL2 are low, this signals a “don't care” value, which will show as a match against any value. This allows some portions of a pattern to be ignored while other portions are compared.
Problems Encountered in Designing TCAM Layouts
As we have seen in the previous drawings, in order to provide storage and comparison circuits for a single bit in TCAM, the design uses four PMOS transistors, twelve NMOS transistors, two power supply lines, a wordline, a matchline four bitlines and two hitlines. For some CAM applications it is also desirable to allow multiple matchline “channels” to pass through each cell in order to allow additional functions, such as prioritization. An array of these cells can take up a great deal of space, so minimizing the required space is a must.
Additionally, the cell aspect ratio (i.e., width to length ratio) needs to be carefully selected so that the necessary wiring uses the least possible number of metal layers for routing over memory at the chip level. Because of the simultaneous search of every bit, CAMs also draw significant amount of current during operation. A very robust power net is therefore essential to proper operation, especially in embedded applications where localized power droops need to be avoided. Finally, for deep submicron (DSM) process technologies, other factors, such as manufacturability and robustness need to be taken into account as well. The above-mentioned reasons therefore call for a judicious selection of the best suitable CAM bitcell layout architecture that addresses the needs mentioned.
Prior Art Solutions
In order to use similar layouts for both binary and ternary CAM cells, current implementations generally make use of a symmetric 6T-SRAM-layout architecture. This allows comparison circuit 202 to be easily connected to both the true internal node 206 and the complementary internal node 208 of the cell 204, as required for binary CAM cells 200 in FIG. 2. FIG. 3 indicates that a ternary CAM is built from two schematically identical 6-T SRAM bitcells 302A and 302B. The prior art layout of bitcell 202/302B is shown in FIG. 4A. This figure shows the symmetric active areas and polysilicon lines for the 6T SRAM 402 and the comparison circuit 404, which is connected to the true internal node. FIG. 4B shows the metal-1 and metal-2 layers for the same device layouts. In FIG. 4A, 6T-SRAM cell 402 is composed of P-type implant regions 406, N-type implant regions 408, 412, and polysilicon gate lines 420, 422, and 424. N-type implant region 412 is used for the NWELL connection. Furthermore, comparison circuit 404 contains N-type implant regions 410 and polysilicon gate lines 426 and 428. Contacts 430–458 from the gates and/or diffusion areas to metal 1 are also shown. FIG. 4B discloses the metal-1 layer, which includes segments 480–494 and the metal-2 layer, which includes segments 470–478; it additionally repeats contacts 430–478 to help provide reference between the two drawings. Here, metal 1 segment 480 is used for VDD power connection and segment 486 is used for VSS connection. Furthermore, metal 1 segment 482 represents the true and segment 484 the complementary internal node of the 6T-SRAM cell. Metal 2 segments 470 and 471 represent the bitlines of the 6T-SRAM cell, while segment 476 represents one of the hitlines of comparison circuit 304 in FIG. 3. Comparing FIG. 4A to the circuit of FIG. 3, gatelines 420, 422 form the gates for transistors P1B, N2B, P2B, N4B, and gateline 424 forms the gates for transistors N1B and N3B. Contacts 438, 440 provide the nodes by which these segments are connected to the internal nodes of the 6T-SRAM cell. Contact 454 connects transistor gates N1B and N3B to the wordline. Contact 452 connects to bitline 470 (BL or BL2), while contact 456 connects to the associated (complementary) bitline 471 (/BL or /BL2). Contact 430 provides a connection to Vdd, which is carried in metal-1 segment 480, while contacts 444, 448 make the connection to Vss metal-1 segment 486. Metal-1 segment 482 ties contacts 432, 440, 442 together to form one of the internal nodes, while segment 420 similarly ties contacts 434, 438, 446 together in another internal node. Within comparison circuit 404, contact 448 is connected to Vss, carried in metal-2 474, and 450 carries matchline ML. Gatelines for transistors N7 and N8 or for N7B and N8B are carried by segment 426, which is connected through contact 458 to /HBL 476, and by gateline 428.
We have discussed how the assembly of building blocks for 6-T SRAM bitcell 402 and comparison circuit 404 forms ternary CAM subblocks 302B. Comparing schematics of binary CAM 200 of FIG. 2 with ternary CAM 300 of FIG. 3, it becomes clear to those skilled in the art that each individual portion 302A or 302B can form a binary cell 200 by either adding transistors N7A and N8A to portion 302A, or transistors N5B and N6B to portion 302B. Hence, assembly of building blocks 402 and 404 can be used to make either a binary CAM array or a ternary CAM array, as will be shown in the following figures. Showing only the substrate level and gatelines, FIG. 5A discloses two BCAM bitcells as they would be laid out for an array. Each BCAM bitcell 500 contains one 6-T SRAM bitcell 504 and two comparison circuits 502. FIG. 5B discloses the same layouts used to form two TCAM bitcells as laid out for an array. Here, each TCAM bitcell 500′ contains two 6-T SRAM bitcells 504 and two comparison circuits 502.
Of interest when the above layout is used in ternary CAM, the 6T-SRAM layout has its bitline connections 452, 456 and bitlines 470, 471 facing the outside border of the SRAM cell and has connection 444 to ground line Vss inside the cell, affecting the ease of contacting this common node. With connections to the bitlines 452, 456 and internal node connections 432, 434, 442, 446 facing the outside of the bitcell, the n-type diffusions for connection circuit transistors N7B, N8B cannot be adjacent to the diffusions for the SRAM n-type transistors. This results in additional island-to-island (i.e., intra-diffusion) spacing requirements that increase the size of the cell without performance benefit. Furthermore, coupling of hitline 476 and bitlines 470, 471 can occur, which can further degrade the performance. An additional disadvantage is the fact that the wordline connection for this prior art, is also placed inside the cell. Therefore, when two SRAM bitcells are used to form a single TCAM bitcell, this results in two separate wordline contacts. This results in additional layout overhead.